Introduction
A n to 2n decoder is a combinatorial logic device which has n input lines and 2n output lines. For each possible combination of n input binary lines, one and only one output signal will be logic 1. Thus, the decoder is a min-term generator in which each output corresponds to one min-term. Decoders are important logic blocks that find a wide variety of applications in the design of digital systems.Input: (log2n)
Example:3-8 decoder
Output: n bits (exactly one output pins is 1, rest of the pins are 0)Input:3 bits representing a binary input number
Figure 1 shows the block diagram of the 3-to-8 decoder.
Output:1 bit corresponding to the value of the binary input number is set to 1Figure 1. Block diagram of a 3-to-8 decoder Truth Table
Figure 2 shows the truth table of a 3-to-8 decoder. Ip0 to Ip2 are the binary input lines and the Op0 to Op7 are the eight output lines.Figure 2. Truth table of 3-to-8 decoder. Verilog Module
Figure 3 presents the Verilog module of the 3-to-8 decoder. The module takes three 1-bit binary values from the three input ports Ip0 to Ip2. The eight 1-bit binary value outputs are presented in eight output ports Op0 to Op7. The decoder function is controlled by using an enable signal, EN.Figure 3. Verilog module of 3-to-8 decoder. Verilog Code for 3-to-8 Decoder (decoder3to8.v)
Figure 4. Verilog Code for 3-to-8 decoder Verilog Test Bench for 3-to-8 Decoder (decoder3to8_tb.v)
Figure 5. Verilog Test-bench for 3-to-8 decoder Timing Diagram
Figure 6. Timing diagram of 3-to-8 decoder
![3 to 8 decoder using 2 to 4 decoder vhdl code 3 to 8 decoder using 2 to 4 decoder vhdl code](/uploads/1/1/1/9/111950285/970989355.png)
VHDL Code for a 8 x 3 Encoder library ieee; use ieee.stdlogic1164.all; entity enc is port(i0,i1,i2,i3,i4,i5,i6,i7:in bit; o0,o1,o2: out bit); end enc; architecture vcgandhi of enc is begin o0VHDL Code for a 3 x 8 Decoder.
Just as Multiplexer, Decoder is also a Combinational circuit which transforms given inputs to a maximum number of outputs (maximum outputs equal to 2n and n are given inputs ).
A block diagram of decoder consists of input lines, one or more enable inputs and a maximum number of output lines.
To construct a decoder, we require to know the number of all possible output lines that totally depends on the given input.
To construct a decoder, we require to know the number of all possible output lines that totally depends on the given input.
So, if n represents given input lines then possible output lines would be 2n.
Decoder with three inputs would give 8 outputs (n=2,23 that is 8).
Decoder with three inputs would give 8 outputs (n=2,23 that is 8).
Here are the steps to construct 3 to 8 decoder
- 3'b110: Dataout = 8'b01000000; 3'b111: Dataout = 8'b10000000; //To make sure that latches are not created create a default value for output. Default: Dataout = 8'b00000000; endcase endmodule Testbench for testing 3:8 Decoder: //This is a testbench code used for testing the 3:8 decoder module. //Since its a testbench code we dont need to.
- Engr354 VHDL Examples 8 Concurrent vs. Sequential VHDL Code. All previous VHDL statements shown are called concurrent assignment statements because order does not matter;. When order matters, the statements are called sequential assignment statements;. All sequential assignment statements are placed within a process statement.
Step 1. Now we know possible outputs for 3 inputs, so construct 3 to 8 decoder, having 3 input lines, a enable input and 8 output lines. In the below diagram, given input represented asI2, I1 and I0 , all possible outputs named as O0, O1, O2,O3, O4, O5,O6& O7 and a E were represented by Enable input.
With Enable input
Without Enable input
Step 2. Now, it turns to construct the truth table for 3 to 8 decoder. E input can be considered as a control input. Mean to say, If E equals to 0 then the decoder would be considered as disabled regardless of what inputs are, If E equals to 1 then the decoder would work as per inputs.
Truth table without E input
Inputs | Outputs | |||||||||
---|---|---|---|---|---|---|---|---|---|---|
I2 | I1 | I0 | O7 | O6 | O5 | O4 | O3 | O2 | O1 | O0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
We can represent the following output as:
![3 to 8 decoder in vhdl code 3 to 8 decoder in vhdl code](/uploads/1/1/1/9/111950285/521131031.jpg)
O0 = I0‘.I1‘.I2‘
O1 = I0.I1‘.I2‘
O1 = I0.I1‘.I2‘
O2 = I0‘.I1.I2‘
O3 = I0.I1.I2‘
O4 = I0‘.I1‘.I2
O5 = I0.I1‘.I2
O6 = I0‘.I1.I2
O7 = I0.I1.I2
O3 = I0.I1.I2‘
O4 = I0‘.I1‘.I2
O5 = I0.I1‘.I2
O6 = I0‘.I1.I2
O7 = I0.I1.I2
Truth table with E input
Inputs | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
E | I2 | I1 | I0 | O7 | O6 | O5 | O4 | O3 | O2 | O1 | O0 |
0 | - | - | - | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Decoder with E
Explanation:
In above diagram, there were three input lines along with their complements using Inverters. Each and every AND gate were holding four inputs from E, I1, I1 and I0 and producing 8 outputs.
4 To 16 Decoder Using 3 To 8 Decoder Vhdl Code
Decoder Without E
2 To 4 Decoder Vhdl
Explanation:
In the above diagram, there were three input lines with their respective complements using Inverters. Each and every AND gate were holding three inputs from I1, I1 and I0 and producing 8 outputs.
In the above diagram, there were three input lines with their respective complements using Inverters. Each and every AND gate were holding three inputs from I1, I1 and I0 and producing 8 outputs.