- VHDL Code For D Flip-Flop; VHDL Code For JK Flipflop; VHDL Code For T Flipflop; VHDL Code For SR Flipflop; VHDL Code For Comparator (4 bit) VHDL Code For 1:4 Demux; VHDL Code For 4:1 Mulitplexer; VHDL Code For 8:1 multiplexer; VHDL Code For 2:4 Decoder; VHDL Code for 3:8 decoder; VHDL Code For Encoder (4:2) CODE STRUCTURE OF VHDL; Introduction.
- 2: 4 Decoder using Logical Gates (Verilog CODE). 08:37 Unknown 5 comments Email This BlogThis!
As you know, a decoder asserts its output line based on the input. For a 3: 8 decoder, total number of input lines is 3 and total number of output lines is 8. Based on the input, only one output line will be at logic high. The verilog code for 3:8 decoder with enable logic is given below. 3:8 Decoder Verilog Code.
library IEEE;
entity deco1 is
y : in STD_LOGIC;
d0 : out STD_LOGIC;
d2 : out STD_LOGIC;
d4 : out STD_LOGIC;
d6 : out STD_LOGIC;
end deco1;
component decand1 is
b : in STD_LOGIC;
d : out STD_LOGIC);
component decnot1 is
c : out STD_LOGIC);
signal s2, s1, s3: STD_LOGIC;
g1: decnot1 port map(x,s1);
g3: decnot1 port map(z,s3);
g5: decand1 port map(s1, s2, z, d1);
g7: decand1 port map(s1, y, z, d3);
g9: decand1 port map(x, s2, z, d5);
g11: decand1 port map(x, y, z, d7);
- TEST BENCH
LIBRARY ieee;
ENTITY deco2_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT deco1
x : IN std_logic;
z : IN std_logic;
d1 : OUT std_logic;
d3 : OUT std_logic;
d5 : OUT std_logic;
d7 : OUT std_logic
END COMPONENT;
--Inputs
signal y : std_logic := '0';
--Outputs
signal d1 : std_logic;
signal d3 : std_logic;
signal d5 : std_logic;
signal d7 : std_logic;
BEGIN
uut: deco1 PORT MAP (
y => y,
d0 => d0,
d2 => d2,
d4 => d4,
d6 => d6,
3 To 8 Encoder Vhdl Code
);
stim_proc: process
x<='0'; y<='0';z<='0';
x<='0'; y<='0';z<='1';
x<='0'; y<='1';z<='0';
x<='0'; y<='1';z<='1'; wait for 100ns;
x<='1'; y<='0';z<='1';wait for 100ns;
x<='1'; y<='1';z<='1';wait for 100ns;
END;